Company Overview
AdoreSys, an ASIC Solution Provider aims to provide best-in-class Automotive ADAS, Autonomous Driving and AI HPC ASIC solution to Car OEM, Datacenter OEM, Tier 1 & Tier 2 chip providers. AdoreSys ASIC platforms are built based on mainly ARM IPs, enriched with in-house optimal PPA & Functional Safety feature sets and highly customizable to cater customer needs.
At AdoreSys, we believe that a strong team is essential for success. Our transparent and collaborative culture enables us to deliver outstanding technical solutions. Strategically positioned around the globe, we effectively serve customers worldwide. Our headquarters is located in Singapore, with R&D centers in Malaysia, Shanghai, and Beijing. These centers are equipped with cutting-edge technology and staffed by experts dedicated to advancing innovation and meeting the diverse needs of our global clientele.
We are committed to ensuring that personal fulfillment and professional growth go hand in hand. Our comprehensive benefits and support programs are designed to promote your physical, mental, and financial well-being, while our emphasis on career development and continuous learning empowers you to thrive alongside some of the brightest minds in the industry.
Join us at AdoreSys, where you’ll be part of a dynamic, forward-thinking company dedicated to your success, happiness, and long-term career growth.
Job Description
As a DFT engineer, you will contribute to
• Development of DFT strategy and architecture design, including hierarchical MBIST, LBIST, SCAN and ATPG.
• Insert DFT logic, including SCAN, MBIST，LBIST and other DFT IP blocks.
• Complete all Test Design Rule Checks and Design changes to fix DRC violations to achieve high test quality.
• Work with Logic Design team, back-end physical design team to develop timing constraints required for DFT implementation.
• Engage in the design equivalence check, DFT pre & post DFT simulation, work with design team develop and verification the In System Test, Chip level MBIST Repair Test.
Qualifications needed
• Experienced in DFT designs.
• Knowledge about industrial standards and practices in DFT, including MBIST, ATPG, SCAN, JTAG/IJTAG and trade-offs between test quality and test time
• Knowledge of industry standards for DFT and design tools (like Mentor Tessent, SynopsysTMAX)
• Solid understanding of design verification methodologies for validating DFT implementation in simulation pre/post-silicon.
• Experience in debugging Compressed ATPG patterns, MBIST，Repair, and IJTAG related issues.
• Have good communication capability and teamwork spirit.Have the ability about logical thinking and sensitive to the problem with good self-study and problem shooting.
Personal Skills
We are proud to have a set of behaviors that reflect our unique culture and guide our decisions, defining how we work together
• Strong desire to delivery result
• Positive, “can do” attitude.
• Self-motivated, dependable, and prompt.
• Flexible, willing to adapt to changing responsibilities and assignments.
• Good communicator, personable.
• Capable of working as a team player.
• Ethical, honest, and trustworthy.
• Fluent in English & Chinese (Mandarin)