岗位职责: Responsibilities: 1.同设计工程师配合，完成IP Level Feature点提取，完成IP Level UVM 验证坏境搭建及验证;Cooperate with design engineers to complete lP Level Feature point extraction, complete lp Level UVM verificationenvironment construction and verification. 2.提取SoCIP集成Feature，完成SoCIP 集成验证; Extract SoC lP inteqration Feature to complete SoC lP integration verification. 3.负责IP环境集成到SoC并在SoC验证: Responsible for lP environment integration into SoC and verification in SoC4.开发验证脚本(时钟，复位，pad等验证脚本); Develop verification scripts (clock, reset, pad, etc.). 4.负责IP后仿验证工作。 Responsible for lP post verification. 要求: Requirements: 1.集成电路，电气工程等专业硕士及以上学历, Master degree or above in lC, electrical engineering, etc. 2.有ASIC,SoC，IP验证环境搭建经验; Experience in building ASlC, SoC, lP verification environment. 3.对UVM验证方法学有深入了解; In-depth understanding of UVM verification methodology. 4.至少有3年的相关工作经验; At least 3 years of relevant work experience. 5.熟练学握Verilog/System Verilog语言; Proficiency in Verilog/System Verilog language. 6.熟悉/ Python/Per 等脚本语言: Familiar with scripting languages such as/ Python / Perl. 7.标准的文档书写能力; Standard document writing skills. 8.熟练使用Linux系统; Proficient in using Linux system. 9.熟练使用英文进行读写。 Proficient in reading and writing in English
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