主管/高级模拟设计工程师(IO&ESD)

Responsibility:

1. Design, simulation and verification of CMOS analog and mixed-signal circuits.

2. Co-work with layout, digital and PR engineer for physical implementation.

3. Help define specifications of IC blocks and create design documentation.

4. Co-work with test team for silicon test, characterization and debugging.

Qualification:

1. MSEE.

2. 5 years+ in Analog IC design;

3. Solid knowledge and experience in IO/ESD circuit design.

4. Experience in large scale SOC design is a plus.

5. Good understanding of FinFET CMOS technology process and device physics.

6. Proficiency of EDA design tools (Virtuoso, Spectre, HSPICE, AMS, etc).

7. Experiences in Verilog, Python, and/or Matlab.

公司地点:上海徐汇区和光天地漕宝路181号

公司简介:

职位发布者:吴经理

澜起科技股份有限公司

融资阶段:

公司规模:

相似职位: